1. Field of the Invention
The present invention relates to metal interconnect layers in a nonvolatile semiconductor memory, which are used for patterning and layout of metal interconnects, such as aluminum (Al) interconnects, tungsten (W) interconnects, or copper (Cu) interconnects, for block-type memory cell transistors such as a NAND EEPROM or an AND EEPROM.
2. Description of the Related Art
FIGS. 1 through 9 show a NAND EEPROM fabricated by a method of the related art of the present invention. FIG. 1 schematically shows an enlarged aerial pattern diagram of a memory cell array region. FIGS. 2 through 4 are schematic cross-sectional diagrams cut along the lines I-I, II-II, and III-III of FIG. 1, respectively. In addition, FIG. 5 shows an overall aerial pattern diagram of the memory cell array region 1. FIG. 6 is a detailed aerial pattern diagram of the memory cell array region 1 formed wide source lines SL2. FIGS. 7 through 9 are schematic cross-sectional diagrams cut along the lines IV-IV, V-V, and VI-VI of FIG. 6, respectively.
As shown in FIG. 1, the nonvolatile semiconductor memory includes data transfer lines BL, data select lines WL disposed orthogonal to the data transfer lines BL, a device region 10 and a device isolating region 12, extending along the data transfer lines BL, select gate lines SSL and SGL, source line contacts CS, data transfer line contacts CB, via contacts 16, a first source line SL0, and second source lines SL2. As shown in FIG. 1, circular or elliptical source line contacts CS and data transfer line contacts CB are aligned orthogonal to the data transfer lines BL. The contacts are aligned along the line III-III in extremely close intervals of 2 to 3F, where F denotes the minimum fabrication dimension depending on the widths of a device region 10 and a device isolating region 12. On the other hand, the data transfer line contacts CB and the source line contacts CS are aligned along the line I-I, which is orthogonal to the line III-III, at longer intervals than the intervals along the line III-III, for example, 40 to 100F in the case of a NAND flash memory. Note that x denotes the width of each of the second source lines SL2, and u denotes the intervals therebetween in FIG. 1.
As shown in FIG. 2, the cross section cut along the line I-I of the nonvolatile semiconductor memory shows a p-well region or a semiconductor substrate 26, diffused layers 18, memory cell transistors 20, select gate transistors SGS and SGD, a barrier insulator film 22, a data transfer line contact CB, a source line contact CS, a first source line SL0, a data transfer line extended region 14, a via contact 16, a data transfer line BL, and interlayer insulator films 23 and 24. Moreover, as shown in FIGS. 3 and 4, the cross-sections cut along the lines II-II and III-III of the nonvolatile semiconductor memory, respectively, show a p-well region or a semiconductor substrate 26, diffused layers 18, a barrier insulator film 22, data transfer line contacts CB, source line contacts CS, a first source line SL0, data transfer line extended regions 14, a first via contact 16, data transfer lines BL, a source shunt line SH1, a well shunt line SH2, a second via contact 17, a second source line SL2, and interlayer insulator films 23 and 27. Note that y denotes the distance between the semiconductor substrate 26 surface and the second source line SL2, and x denotes the width of the second source line SL2 in FIG. 4.
The data transfer line contacts CB and the first via contact 16 are filled with phosphorus (P) or the like highly-doped polycrystalline silicon or a metal such as W, and the data transfer line extended regions 14 and the first source line SL0 are filled with a metal such as W. Accordingly, the data transfer line extended regions 14, being longer than 7F along the data transfer lines BL, are considered as the interconnect layers. Alternatively, a linear, longer fine metal pattern is naturally available for the interconnect layers, and the following description is also applicable to a configuration where the first via contacts 16 and the data transfer line extended regions 14 are omitted, and contacts are directly formed by regarding the data transfer lines BL as the interconnects. The data transfer lines BL, the second via contact 17, and the second source lines SL2 are made of a metal such as Al, Cu, or the like.
The data transfer lines BL are aligned orthogonal to the line III-III in extremely close intervals of 2 to 3F where F denotes the minimum fabrication dimension, forming a single memory cell array block with approximately five hundred thirty data transfer lines BL, for example. Assuming that serially aligned 16-bit memory cell transistors form a single NAND memory cell unit, for example, a single NAND memory cell block includes five hundred thirty NAND memory cell units arranged in parallel along the line II-II. In addition, the source shunt line SH1, which is connected to the contact SB for the semiconductor substrate 26 and the contacts for the source line SL, and the well shunt line SH2, which is connected to the contact for the well, are disposed between the memory cell array blocks (e.g., for approximately every five hundred thirty data transfer lines BL). Note that the source line SL0 is formed along the line II-II, which is used as the ground interconnect for the source line SL between the data transfer lines BL. In addition, as shown in the cross section cut along the line II-II, the source line SL2 is used as the ground interconnect for the source line extending along the line I-I orthogonal to the line II-II. The source line SL2 and the source line SL0 allow formation of grid-shaped ground interconnects formed by the source lines. For example, the interconnect of approximately 15 to 20F wide, which is the source line SL2, is disposed to extend along the line I-I above the source shunt line SH1 so that it does not overlap the area of the memory cell array. In addition, assuming that serially aligned 16-bit memory cell transistors disposed between the bit line side select gate transistor SGD and the source line side select gate transistor SGS form a single NAND memory cell unit, approximately 2048 blocks are disposed along the line I-I; therefore, it is considered that the source line SL2 becomes a sufficiently long interconnect in order to realize the approximately 2048 blocks as an example.
A first problem of the related art is an increase in the interconnect resistance due to a decrease in the space between the memory cell arrays and a decrease in the interconnect width due to miniaturization. When the source line SL2 is linearly disposed between the memory cell arrays as in the related art, a decrease in the space between the memory cell arrays refers to a decrease in the source interconnect width that can be provided therebetween. In addition, when further miniaturization is required, miniaturization of the interconnect results in a decrease in the space between the memory cell arrays; however, since the interconnect width is reduced in either case, it is impossible to prevent the interconnect resistance from increasing.
As shown in FIG. 5, the overall aerial pattern of the memory cell array region is configured with a semiconductor chip 6, a memory cell array region 1 indicated by a dashed line, source lines SL2, data select line control circuits 2, a sense amplifier or a data latch 4, source line shunt transistors 3, and a power supply interconnect pad 5. As particularly shown in FIG. 5, when the power supply interconnect pad 5 region is disposed on only one side of the semiconductor chip 6, a thick power supply interconnect cannot be disposed on the periphery when the chip area is reduced. This is because the data select line control circuits 2 and the sense amplifier or the data latch 4 are formed close to the memory cell array region 1. Especially, in the case of a nonvolatile semiconductor memory that erases data by having positive potential applied to the p-well region 26 in which the memory cell array region 1 is formed, the second source lines SL2 connected to the memory cell transistors must be kept at a positive voltage greater than the voltage of the p-well region 26 so as to prevent leakage current from the source lines SL2 from developing. Therefore, as shown in FIG. 5, the source line shunt transistors 3 are needed on the periphery of the memory cell array region 1 to bring the source lines SL2 and the power supply interconnect pad 5 at ground potential into or out of conduction. It is desirable for reduction in the interconnect area and the chip area that the source line shunt transistors 3 be disposed on only one side of the memory cell array, so as to permit reduction in the thick interconnect area between the source line shunt transistors 3 and the power supply interconnect pad 5. In this case, in the memory cell array region 1 disposed in the upper portion of FIG. 5, since the source lines SL2 are long interconnects almost equivalent to the length of one side of the semiconductor chip 6, serious problems occur, such as a drop in voltage due to the interconnect resistance and, depending on location, a change in memory cell transistor operation. For example, such drop in voltage may cause an increase in the source line voltage when reading during a write-verify operation, resulting in an apparent increase in write threshold voltages (e.g., see Japanese Patent Application Laid-Open No. Hei 11-260076). More specifically, disposing the memory cell array in this location may cause an insufficient programming in a memory cell transistor using multi-value thresholds requiring precise threshold control.
A second problem is that the source lines SL2 partially cover NAND strings in the memory cell array region 1 when the width of each source line SL2 is increased so as to reduce the interconnect resistance for solving the first problem. FIGS. 6 through 9, which correspond to FIGS. 1 through 4, show the case of making the width of each source line SL2 wider where the source lines SL2 partially cover the NAND strings. In particular, FIG. 9 shows the cross section of a region where the source lines SL2 in the corresponding cross section in FIG. 4 cover the NAND strings. Note that description of the components based on the related art in FIGS. 6 through 9, which are substantially the same as those shown in FIGS. 1 through 4, is omitted. There is a difference in that the width of each second source line SL2 is extended to the memory cell array region 1 so as to be wider and an SiN film 7 is used as an uppermost passivation film.
According to the related art, as shown in FIG. 1 and FIG. 4, if y denotes the distance between the source line SL2 and a tunnel insulator film 44 (see FIGS. 10 and 11 for enlarged diagrams) in a memory cell transistor, x denotes the width of each of the source lines SL2, and u denotes the distance therebetween, the width of each source line SL2 (x) and the space therebetween (u) have been made wider-so as to satisfy y<x/2 and y<u/2 and reduce the source line SL2 resistance. A passivation film such as the silicon nitride film (SiN film) 7 is typically formed after formation of the source lines SL2, and hydrogen developed during that formation is diffused into the memory cell transistors. When the source lines SL2 do not cover the memory cell array region 1, diffused hydrogen easily reaches the tunnel insulator film 44 or the gate insulator film of the select gate transistor SGD or SGS, and is then trapped in the tunnel insulator film 44 or the gate insulator film, resulting in restoration of a part of the defects of the tunnel insulator film 44 or the gate insulator film. In addition, since the interface between the tunnel insulator film 44 or the gate insulator film and the semiconductor substrate 26 is also contacted by the diffused hydrogen, the interface state is terminated, the threshold of an nMOS transistor decreases, and the subthreshold coefficient decreases. On the other hand, when the source lines SL2 overlap the memory cell array region 1, diffused hydrogen is trapped in a barrier metal layer of the source lines SL2 made of Ti, TiN, or the like, and does not reach the tunnel insulator film 44 or the gate insulator film. More specifically, in the case of isotropic diffusion of hydrogen as with the case of forming a passivation film such as the SiN film 7 and then carrying out a thermal treatment, when y<x/2 is satisfied, the diffused hydrogen may reach the tunnel insulator film 44 or the gate insulator film in the region where no source line SL2 is formed, when the hydrogen diffusion length is between y and x/2; whereas, the diffused hydrogen may not reach the tunnel insulator film 44 in the center of the source line SL2. Accordingly, it is apparent that the hydrogen density distribution in the tunnel insulator film 44 is location dependent. As a result, there is a problem of the difference in reliability of NAND strings of memory cell transistors with the source lines SL2 formed thereover and not formed thereover. In addition, when anisotropic etching (RIE) is used to process the source lines SL2, the probability of forming the source lines SL2 over the NAND strings greatly differs. As a result, since the etched region is damaged due to etching ions, a problem of the difference in memory cell transistor reliability also arises.
Furthermore, in the case of FIGS. 6 through 9, the electrical capacitance of the data transfer lines BL, which are connected to the NAND strings covered by the source lines SL2, relative to the source lines SL2, is extremely increased for the number of NAND strings multiplied by the number of NAND blocks in comparison with data transfer lines BL connected to the NAND strings, which are covered by no source line SL2. This causes a variation in the value of the electrical capacitance among the data transfer lines, resulting in differences in RC time constant among the data transfer lines during reading, where R denotes the value of the parasitic resistance of the data transfer line and C denotes the value of the parasitic capacitance of the data transfer line. Therefore, a greater timing margin for reading is needed.
The metal interconnects of on the related art are linearly disposed between the memory cell arrays, which are formed with the minimum fabrication dimension, without covering the memory cell arrays. However, there has been a problem of an increase in the metal interconnect resistance due to miniaturization of the metal interconnects and the spaces between the memory cell arrays as miniaturization increases.